module PC (
    input [15:0] PC_next,
    input clk,RST,
    output reg [15:0] PC
);

    always @(posedge clk) begin
        if (RST == 1'b1) begin
            PC <= 16'h0;
        end
        else begin
            PC <= PC_next;
        end
    end
    
endmodule